Methods and apparatuses for dynamic memory termination
US9153296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2012 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Jun 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.