Memory array device and method for reducing read current of the same
US9153322B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Dec 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array device is disclosed, which includes a plurality of memory array rows, each memory array row including a plurality of subsidiary memory arrays and a switch arranged between every adjacent two subsidiary memory arrays; wherein each subsidiary memory array includes: a memory unit for storing a data; a programming indication bit arranged prior to the memory unit for indicating whether the subsidiary memory array has been programmed; and an inversion indication bit arranged subsequent to the memory unit for indicating whether a data had been inverted before being written in the memory unit of the subsidiary memory array. A method for reducing a read current of a memory array device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.