Page buffer circuit
US9153328B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2014 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Jun 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.