Patent · US Active

Methods for the formation of a trap rich layer

US9153434B2 · kind B2 · utility

7Cited by

19References

21Claims

0Family size

Assignee

Silanna Semiconductor U.S.A., Inc. · US

Inventors

Chris Brindle · Poway, US
Michael A. Stuber · Carlsbad, US
Stuart B. Molin · Carlsbad, US

Key dates

Filing date	Sep 5, 2014
Grant date	Oct 6, 2015
Priority date	—
Expiry date	Sep 5, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1421
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.