Wafer processing
US9153473B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2013 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Sep 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V40/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods for forming a device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layers of the top and bottom pad stacks include an initial thickness TT1 and TB1 respectively. Trench isolation regions are formed in the substrate. The second pad layer of the top and bottom pad stacks are removed after forming the trench isolation regions by a batch wet etch process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.