System and method for through silicon via yield
US9153506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2012 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Jan 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.