Multi-chip package and interposer with signal line compression
US9153508B2 · kind B2 · utility
6Cited by
15References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2012 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Oct 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15788
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip package with signal line compression for testing of the multi-chip package. The multi-chip package includes an interposer and two or more integrated circuits attached to the interposer. The interposer includes multiple data signal lines for data communications between the two integrated circuits. The data signal lines are also coupled to one or more test contacts through an interface circuit. The number of test contacts is smaller than the number of signal lines, which allows a large number of signal lines to be tested with a smaller number of test contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.