Torsten Partsch
54Patents
11h-index
34Co-inventors
78Inventor score
Filing activity: Jun 29, 2000 → Apr 29, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7028234B2 | Method of self-repairing dynamic random access memory | Physics | 81 | Expired |
| US7079441B1 | Methods and apparatus for implementing a power down in a memory device | Physics | 77 | Expired |
| US6847911B2 | Method and apparatus for temperature throttling the access frequency of an integrated circuit | Physics | 46 | Expired |
| US7031205B2 | Random access memory with post-amble data strobe signal noise rejection | Physics | 44 | Expired |
| US7345931B2 | Maintaining internal voltages of an integrated circuit in response to a clocked standby mode | Physics | 28 | Expired |
| US6760261B2 | DQS postamble noise suppression by forcing a minimum pulse length | Physics | 17 | Expired |
| US6259652A | Synchronous integrated memory | Physics | 15 | Expired |
| US6351167B1 | Integrated circuit with a phase locked loop | Electricity | 14 | Expired |
| US6584021B2 | Semiconductor memory having a delay locked loop | Physics | 13 | Expired |
| US6661265B2 | Delay locked loop for generating complementary clock signals | Electricity | 12 | Expired |
| US6809914B2 | Use of DQ pins on a ram memory chip for a temperature sensing protocol | Physics | 11 | Expired |
| US6653875B2 | Method and apparatus for a delay lock loop | Electricity | 9 | Expired |
| US6272035A | Integrated memory | Physics | 9 | Expired |
| US6696872B1 | Delay locked loop compensating for effective loads of off-chip drivers and methods for locking a delay loop | Emerging Cross-Sectional Technologies | 9 | Expired |
| US7016452B2 | Delay locked loop | Electricity | 9 | Expired |
| US6285228A | Integrated circuit for generating a phase-shifted output clock signal from a clock signal | Electricity | 8 | Expired |
| US6285176A | Voltage generator with superimposed reference voltage and deactivation signals | Physics | 7 | Expired |
| US9153508B2 | Multi-chip package and interposer with signal line compression | Electricity | 6 | Active |
| US6275445A | Synchronous integrated memory | Physics | 6 | Expired |
| US7289374B2 | Circuit and method for adjusting threshold drift over temperature in a CMOS receiver | Physics | 6 | Expired |
| US6777990B2 | Delay lock loop having an edge detector and fixed delay | Electricity | 6 | Expired |
| US6388944B2 | Memory component with short access time | Physics | 6 | Expired |
| US6480024B2 | Circuit configuration for programming a delay in a signal path | Electricity | 5 | Expired |
| US6711091B1 | Indication of the system operation frequency to a DRAM during power-up | Physics | 5 | Expired |
| US6670802B2 | Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits | Physics | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.