Surrounding gate transistor (SGT) structure
US9153697B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2011 |
| Grant date | Oct 6, 2015 |
| Priority date | — |
| Expiry date | Nov 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.