Architecture for storage of data on NAND flash memory
US9158675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Aug 21, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.