Patent · US Active

Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses

US9158696B2 · kind B2 · utility

0Cited by

4References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ilhyun Kim · Seoul, KR
Alexandre J. Farcy · Hillsboro, US
Choon Wei Khor · Air Itam, MY
Robert L. Hinton

Key dates

Filing date	Dec 29, 2011
Grant date	Oct 13, 2015
Priority date	—
Expiry date	Jun 9, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0862
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses. This allows overlapping the ITLB and IC miss stall cycles with older instruction byte reads or older IC misses, resulting in fewer stalls than previous implementations and improved performance

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.