Memory core and semiconductor memory device including the same
US9159398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2014 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Jun 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.