Control circuit of SRAM and operating method thereof
US9159403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | May 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.