Semiconductor memory device having bouncing detection circuit and method of operating the same
US9159435B2 · kind B2 · utility
6Cited by
1References
14Claims
0Family size
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Key dates
| Filing date | Aug 31, 2012 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device includes a memory cell array that includes a plurality of cell strings coupled between a common source line and a plurality of bit lines, a peripheral circuit that reads data stored in a selected memory cell, a bouncing detection circuit that compares a voltage supplied to the common source line and a reference voltage to thereby output a detection signal while performing a reading operation, and a control circuit that controls the peripheral circuit in order to perform the reading operation by adjusting the number of sensing operation times in accordance with the detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.