Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure
US9159667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Aug 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.