Die stacking system and method
US9159694B2 · kind B2 · utility
0Cited by
8References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2010 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Die stacking systems and methods are disclosed. In an embodiment, a semiconductor device includes a passivation surface and a conductive die receiving surface located in an opening of the passivation surface. The conductive die receiving surface has a surface area that is larger than a footprint of a second die that is electrically coupled to the conductive die receiving surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.