Clock edge detection device and method
US9160322B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2014 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Jun 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.