Faulty core recovery mechanisms for a three-dimensional network on a processor array
US9160617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2012 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Sep 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/557
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.