Cycling endurance extending for memory cells of a non-volatile memory array
US9164836B2 · kind B2 · utility
12Cited by
0References
27Claims
0Family size
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Key dates
| Filing date | Dec 28, 2011 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Jun 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.