Inventor · Redwood City, CA, US

Ravi Kumar

30Patents
5h-index
37Co-inventors
65Inventor score

Filing activity: Dec 28, 2011 → Jul 27, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9857992B2 Dynamic window to improve NAND endurance Physics 34 Active
US9164836B2 Cycling endurance extending for memory cells of a non-volatile memory array Physics 12 Active
US9330784B2 Dynamic window to improve NAND endurance Physics 10 Active
US10705966B1 Mapping for multi-state programming of memory devices Physics 5 Active
US11404127B1 Read refresh to improve power on data retention for a non-volatile memory Physics 5 Active
US11361834B1 Systems and methods for dual-pulse programming Physics 5 Active
US11342035B1 Memory apparatus and method of operation using one pulse smart verify Physics 2 Active
US11508440B1 Periodic write to improve data retention Electricity 1 Active
US11177002B1 Programming memory cells using encoded TLC-fine Physics 1 Active
US11475961B1 Nonvolatile memory with efficient look-ahead read Physics 1 Active
US11475967B1 Modified verify in a memory device Electricity 1 Active
US11568943B2 Memory apparatus and method of operation using zero pulse smart verify Physics 1 Active
US11372765B2 Mapping for multi-state programming of memory devices Physics 1 Active
US11398280B1 Lockout mode for reverse order read operation Electricity 1 Active
US11302409B2 Programming techniques including an all string verify mode for single-level cells of a memory device Physics 0 Active
US10990311B2 Multi-stream non-volatile storage system Physics 0 Active
US12046306B2 Temperature dependent programming techniques in a memory device Physics 0 Active
US12099728B2 Non-volatile memory with programmable resistance non-data word line Physics 0 Active
US11417393B2 Two-stage programming using variable step voltage (DVPGM) for non-volatile memory structures Physics 0 Active
US12254218B2 Read schemes with adjustment for neighboring word line sanitization Physics 0 Active
US11574693B2 Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention Physics 0 Active
US12027218B2 Location dependent sense time offset parameter for improvement to the threshold voltage distribution margin in non-volatile memory structures Electricity 0 Active
US11972809B2 Selective inhibit bitline voltage to cells with worse program disturb Electricity 0 Active
US11557358B2 Memory apparatus and method of operation using adaptive erase time compensation for segmented erase Physics 0 Active
US11409443B2 Intelligent memory wear leveling Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.