Patent · US Active

Processor arrangements and a method for transmitting a data bit sequence

US9165162B2 · kind B2 · utility

0Cited by

1References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Franz Klug · Munich, DE
Steffen Sonnekalb · Munich, DE

Key dates

Filing date	Dec 28, 2012
Grant date	Oct 20, 2015
Priority date	—
Expiry date	Sep 5, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/64
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.