Patent · US Active

Method of using a PMOS pass gate

US9165640B1 · kind B1 · utility

0Cited by

13References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Jun Liu · 红钢城街道, CN
Albert Ratnakumar · San Jose, US
Irfan Rahim · Milpitas, US
Qi Xiang · San Jose, US

Key dates

Filing date	Jul 17, 2014
Grant date	Oct 20, 2015
Priority date	—
Expiry date	Jul 17, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2217/0054
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.