Low voltage dual supply memory cell with two word lines and activation circuitry
US9165642B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 2013 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Jul 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.