Nonvolatile memory device having page buffer units under a cell
US9165654B1 · kind B1 · utility
3Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2014 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Aug 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a cell array, a distributed page buffer including a plurality of page buffer units disposed below the cell array, the plurality of page buffer units having a certain size; and a distributed page buffer control circuit including a plurality of page buffer control circuit units, each page buffer control circuit unit being arranged at one side of a corresponding page buffer unit, and configured to control operations of the corresponding page buffer unit, the plurality of page buffer control circuit units each having a predetermined size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.