Making electrical components in handle wafers of integrated circuit packages
US9165793B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2014 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | May 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.