Fan-out semiconductor package with copper pillar bumps
US9165877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2013 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Dec 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.