Vertical channel type nonvolatile memory device and method for fabricating the same
US9165924B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Mar 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
Abstract
A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.