Low power inverter circuit
US9166585B2 · kind B2 · utility
2Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2014 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Aug 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.