Adjustable impedance matching network
US9166640B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2012 |
| Grant date | Oct 20, 2015 |
| Priority date | — |
| Expiry date | Jun 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/15
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An adjustable impedance matching network includes a first terminal, a second terminal, a reference potential terminal, a transmission line transformer with a first inductor path and a second inductor path. A semiconductor switching element is configured to bridge a sub-section of the first inductor path or the second inductor path to thereby adjust an inductance of the first inductor path or the second inductor path. According to an alternative embodiment, the impedance matching network includes a selector switch to selectively connect one of a plurality of inductor nodes with at least one of the first terminal and the second terminal. Further embodiments relate to an integrated circuit for adjustable impedance matching with a transmission line transformer formed by first and second inductor paths that are implemented as conductive paths at or in a substrate of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.