Providing extended cache replacement state information
US9170955B2 · kind B2 · utility
51Cited by
11References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2012 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | May 2, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.