Semiconductor hold time fixing
US9171112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.