Memory with multiple levels of data retention
US9171616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jan 27, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.