Methods of manufacturing semiconductor devices including capped metal patterns with air gaps in-between for parasitic capacitance reduction
US9171755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.