Methods for fabricating integrated circuits using self-aligned quadruple patterning
US9171764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2013 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Dec 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.