Dual-damascene process to fabricate thick wire structure
US9171778B2 · kind B2 · utility
4Cited by
16References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jan 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.