Top electrode blocking layer for RRAM device

US9172036B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Hsia-Wei Chen · Taipei, TW
• Wen-Ting Chu
• Kuo-Chi Tu · Baoshan, TW
• Chih-Yang Chang · 員林市, TW
• Chin-Chieh Yang · New Taipei, TW
• Yu-Wen Liao · New Taipei, TW
• Wen-Chun You · Zilongting, TW
• Sheng-Hung Shih · Hsinchu, TW

Key dates

• Filing date: Nov 22, 2013
• Grant date: Oct 27, 2015
• Expiry date: Nov 22, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8836

Abstract

An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.