Electrostatic discharge protection circuit having high allowable power-up slew rate
US9172241B2 · kind B2 · utility
3Cited by
2References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Apr 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A technique for providing electrostatic discharge (ESD) protection in complementary metal-oxide semiconductor (CMOS) technologies is disclosed. A power supply RC-based ESD protection circuit having an RC value in the nanosecond range increases the allowable power-up slew rate so that fast power-up events (e.g., hot-plug and power switching operations) are not erroneously interpreted as ESD events. Because the RC value is small, the layout area needed for the RC-based ESD protection circuit is also reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.