Overlay sampling methodology
US9176396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Jul 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01B11/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.