Patent · US Active

Dual-edge gated clock signal generator

US9176522B1 · kind B1 · utility

0Cited by

8References

15Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Amit Kumar Dey · Noida, IN
Himanshu Mangal · Agra, IN
Kulbhushan Misri · Barwala, IN
Amit Roy · Noida, IN
Vijay Tayal · Noida, IN
Chetan Verma · Sunnyvale, US

Key dates

Filing date	May 2, 2014
Grant date	Nov 3, 2015
Priority date	—
Expiry date	May 17, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/20
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.