Least recently used mechanism for cache line eviction from a cache memory
US9176879B2 · kind B2 · utility
3Cited by
1References
17Claims
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Key dates
| Filing date | Jul 19, 2013 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Jan 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for evicting a cache line from a cache memory includes first selecting for eviction a least recently used cache line of a group of invalid cache lines. If all cache lines are valid, selecting for eviction a least recently used cache line of a group of cache lines in which no cache line of the group of cache lines is also stored within a higher level cache memory such as the L1 cache, for example. Lastly, if all cache lines are valid and there are no non-inclusive cache lines, selecting for eviction the least recently used cache line stored in the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.