Increased error correction for cache memories through adaptive replacement policies
US9176895B2 · kind B2 · utility
1Cited by
18References
17Claims
0Family size
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Key dates
| Filing date | Mar 16, 2013 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Oct 18, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.