Lithography using high selectivity spacers for pitch reduction
US9177797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2013 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Dec 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.