Preventing contamination in integrated circuit manufacturing lines
US9177843B2 · kind B2 · utility
0Cited by
24References
20Claims
0Family size
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Inventors
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Jun 9, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S414/139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.