Method for fabricating semiconductor device having multiple threshold voltages
US9177865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | May 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods for fabricating a semiconductor device. A gate dielectric layer is formed on a substrate including first through third regions. A first functional layer is formed on only the first region of the first through third regions. A second functional layer is formed on only the first and second regions of the first through third regions. A threshold voltage adjustment layer is formed on the first through third regions. The threshold voltage adjustment layer includes a work function adjustment material. The work function adjustment material is diffused into the gate dielectric layer by performing a heat treatment process with respect to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.