Isolation region gap fill method
US9177955B2 · kind B2 · utility
4Cited by
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13Claims
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Key dates
| Filing date | Mar 8, 2013 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Mar 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.