Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning
US9178502B2 · kind B2 · utility
3Cited by
2References
9Claims
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Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Dec 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay line has at least four delay stages coupled together in a series, two multiplexers, and a phase interpolator. The first multiplexer has a first input coupled to an output of the first delay stage, and a second input coupled to an output of the third delay stage. Similarly, the second multiplexer has a first input coupled to an output of the second delay stage, and a second input coupled to an output of the fourth delay stage. The phase interpolator is coupled to outputs of the first and second multiplexers, and has an output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.