Analog-to-digital converter and control circuit with a low quiescent current at low load
US9178522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2014 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Sep 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/802
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.