Verification of connectivity of signals in a circuit design
US9183334B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2014 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Jul 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for verifying connectivity of signals in a circuit design include generating a configured version of the circuit design based on input parameter values. The configured version specifies connections from source pins of ports of circuit blocks of the configured version to destination pins of ports of circuit blocks. Expected source-destination connections between source pins and destination pins of the ports of the circuit blocks of the configured version are determined from the input parameter values. A connectivity checker that includes HDL code is generated based on the expected source-destination connections. For each of the expected source-destination connections, the HDL code forces a first signal value on a source pin of the expected source-destination connection in the configured version of the circuit design and determines whether or not a second signal value at a destination pin of the expected source-destination connection matches the first signal value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.