Instruction set architecture with secure clear instructions for protecting processing unit architected state information
US9183399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | May 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit arrangement utilize secure clear instructions defined in an instruction set architecture (ISA) for a processing unit to clear, overwrite or otherwise restrict unauthorized access to the internal architected state of the processing unit in association with context switch operations. The secure clear instructions are executable by a hypervisor, operating system, or other supervisory program code in connection with a context switch operation, and the processing unit includes security logic that is responsive to such instructions to restrict access by an operating system or process associated with an incoming context to architected state information associated with an operating system or process associated with an outgoing context.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.