Semiconductor memory device
US9183893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 5, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/73
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.